Improper Use of an Inverter

I woke up this afternoon after a good noon nap. I don’t have anything to do to end this day…. err, actually I have some home work assignments, but I’m really not in the mood to do that. I’m not an artist, but most of the time, I need mood to start my work, and right now I dont have that. So I decided to have some fun with inverter.

I designed an inverter using two MOS (duh, obviously) based on 0.5 micron technology from MOSIS. It’s so simple that anyone can do it, just connect both of the Gate as an input, and connect both of the Drain as an output, connect nMOS source to VSS and pMOS source to VDD and you’re done.

shematic
design schematic and it’s testbench circuit

To make sure that the thing I’ve just designed is an inverter, let’s do some analysis, namely DC analysis and Transient analysis. We need a MOS model for this, and MOSIS is generously provided us just that. First of all, let’s do a DC analysis to find out our inverter DC characteristics. We just need to create a testbench circuit, connect VDD and VSS to a 5 volt DC supply, connect input to an arbitrary signal (here I’m using sinusoidal which will be useful for the next analysis). Let’s do a DC sweep this input from 0 to 5 volt and you will have a DC transfer curve at the output of the inverter. Don’t forget to add a load capacitor at the output.

dc-sweep
dc sweep analysis

As you can see from the image, the input and the output is crossed at approximately 2.5184 volt input, this is the Q point or the DC operating point. If our inverter is ideal inverter, then it will have Q point at 2.5 volt, but in the real world, nMOS and pMOS is often mismatch and we have slightly drifted Q point. Let’s adjust our sine wave input with this new operating point. Now, usually an inverter is used to invert input signal in digital circuit. High voltage input becomes low, low input becomes high. You can see this property at the DC curve. If the input is less than, let’s say 1 volt, then the output is saturated at 5 volt. In reverse, if the input is more that 4 volt, the output is saturated at 0 volt. Any voltage level besides that is mapped based on the curvy curve in the middle. But, if we take a closer look, we have a pretty linear line with negative gradient at input in range 2.45 volt to 2.55 volt. The high gradient indicates that if we carefully adjust our input at this range, the inverter would have an amplifier property. The amplification factor is proportional with this gradient.

To prove it, let’s use our sinusoidal signal input. The input is only 5 milivolt carefully placed at the Q point. By using Transient analysis we can see that the output is amplified (and inverted) by some amount. Eureka! we have made the most primitive form of an amplifier😀 .

dc-sweep-tran
transient analysis to prove the amplifier property

Usually in analog design, the inverter design is slightly changed. The pMOS gate is connected to the VDD to create a current source. The amplifier is the nMOS itself. By this modification, it will create a stable and predictable amplifier. But I won’t do that because it will spoil the fun.

After we have proved that our design is correct, the next step is layout. layout is process of drawing in controlled manner. It’s basically a combination of art and design rule. It’s often frustrating but also beautifully captivating at the same time. The layout of inverter is simple, just draw some boxes defining nMOS active region, another boxes for pMOS active region and connect the with polysilicon and metal and you’re done.

layout
layout is finished

To make sure that our design won’t lump together into a glob of metal and poly when it’s being fabricated, we need to do a DRC. It check our layout whether it’s has violate certain rule or not. Maybe the metal width is too small, the via spacing is too close, etc. If we made it correctly, then there would be zero error. Error is not a a bad thing. Just made the apropriate corrections and don’t make the same mistake again.

drc-check
no design violation detected

Error is not a a bad thing. Just made the apropriate corrections and don’t make the same mistake again.

The last step is an LVS. It confront betweeen our initial schematic and our layout design whether we make the same circuit or not. The process is simple, just extract the layout into SPICE netlist, do the same for the schematic, and compare them. Do not extract the parasitic component because the LVS won’t find the equivalent in the schematic. Just extract the intended component (usually only the MOS transistor). If the LVS says that our design match then of you go, we can fabricate it. If not, the the little creature that you’ve created is not an inverter. In my inverter design, it says that the circuits are topologically equivalent. It means that I’ve make the correct circuit but both of them has different parameter. I checked the warning, and I found that the AS, AD, PD, PS parameter is different. It’s expected because I’m using MOSIS parameter for the schematic. But for the layout, I’m using standard 0.5 micron design parameter because MOSIS won’t give theirs. Topologically equivalent is good enough for me.

lvs-check
an lvs confrontation

That’s it, just export the layout into GDSII file, and submit it to MOSIS. Email them that we use ON Semi 0.50 micron (C5) fabrication process. Few months later, we will have this cute little inverter in our hands. Of course you have to pay them few (read: a lot) dollars for their service. Maybe next time I’ll design a ‘real’ circuits. It won’t be one night work though.

3 Comments

  1. newbensagung
    Posted Mei 6, 2010 at 7:31 pm | Permalink | Balas

    bang syafiq..itu design layoutnya pake software apa??dah lama ga bahas rangkaian kayak gini. hehehe.

  2. newbensagung
    Posted Mei 9, 2010 at 4:27 pm | Permalink | Balas

    hahaha

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